The present invention relates to digital logic circuits, and more particularly to a divide by 15 clock circuit.
Phase Locked Loops (PLL) are commonly used in digital communication systems, such as telecommunications networks. To provide reliable locking to clocked digital (asynchronous signals), the phase locked loop requires an accurate reference input clock. Known telecommunication systems typically include a clock operating at 667 Mhz.
It would be advantageous to utilize the existing clock, for example in a telecommunication network, to generate an appropriate reference input clock for the phase locked loop. There are different ways of generating a reference input clock for the phase locked loop. One approach would involve dividing the 667 MHz clock by say 30 to produce a reference input clock of 22 Mhz. Another approach would involve dividing the 667 MHz clock to produce a reference input clock of 44 Mhz. This effectively involves dividing the 667 MHz clock by 15 using a divider circuit. Divide-by-N counters are used in applications where the number N of counts cannot be expressed in binary form, i.e. count to a base N which is not a power of 2, for example, count to the base 10 according to the decimal system. A divide-by-15 circuit may be implemented as a divide-by-3 counter circuit followed by a divide-by-5 circuit. This approach has the advantage that the divide-by-5 circuit may be operated at a lower speed.
The first approach described above would likely suffer from jitter for the higher speed reference input clock for the phase locked loop. The second approach while providing a divide-by-15 function suffers drawbacks. First, it is necessary to balance to more than one clock tree. Secondly, it is more difficult to retire the signal outside of the device with the divide-by-3 and the divide-by-5 counter circuits. Thirdly, this approach is not desirable in terms of xe2x80x9cdesign for testabilityxe2x80x9d or DFT because there would be flip flops in the device clocked by two separate clocks. Lastly, typical implementations result in numerous additional logic gates to the flip flop devices.
Accordingly, there remains a need for a divide-by-15 circuit which overcomes these shortcomings while preferably minimizing the number of logic gates between the flip flop devices in order to meet the timing requirements of digital circuits operating at frequencies in the 0.5 GigaHertz range.
The present invention provides a divider circuit which generates an output signal with a 50% duty cycle and which is suitable as a reference signal for a phase locked loop circuit in digital communication networks.
The divider circuit is suitable for implementation as part of an ASIC device.
In a first aspect, the present invention provides a clock divider circuit having (a) an input port for receiving an input clock; (b) a linear shift register having a plurality of stages, each of the stages comprising a flip flop device and having a data input port, a data output port, and a clock input port, the clock input ports are coupled to the input port, and the stages are connected in series with the data output port of the previous stage coupled to the data input port of the subsequent stage; (c) a feedback loop couples the data output port of the last stage to the data input port of the first stage, and the feedback loop includes a logic gate having an output connected to the data input port of the first stage and a first input connected to the data output port of the last stage and a second input connected to the data output port of the second last stage in the linear shift register; (d) the stages in the linear shift register are operable to shift data at the data input ports to the data output ports and in the feedback loop in response to the input clock; (e) an output port for outputting an output clock signal derived from the data output of the linear shift register.
In another aspect, the present invention provides a clock divider circuit having (a) an input port for receiving an input clock; (b) a linear shift register having a plurality of stages, each of the stages has a data input port, a data output port, and a clock input port, the clock input ports are coupled to the input port, and the stages are connected in series with the data output port of the previous stage coupled to the data input port of the subsequent stage; (c) a feedback loop couples the data output port of the last stage to the data input port of the first stage, and the feedback loop includes a logic gate having an output connected to the data input port of the first stage and a first input connected to the data output port of the last stage and a second input connected to the data output port of the second last stage in the linear shift register; (d) the stages in the linear shift register are operable to shift data at the data input ports to the data output ports and in the feedback loop in response to the input clock; (e) an output port for outputting an output clock signal derived from the data output of the linear shift register; (f) a scan test mode control port; (g) a scan data input port for receiving scan test input data; (h) a scan data output port for outputting scan test output data from the linear shift register; (i) some of the stages including a scan test mode control input, and a scan test data input, the scan test mode control inputs are connected to the scan test mode control port, and at least one of the scan test data inputs are connected to the scan data input port, and the stages are operable to produce scan test output data in response to a scan test mode signal applied to the scan test mode control port.
In a further aspect, the present invention provides clock divider implemented as a circuit on an ASIC device, the clock divider circuit comprises: (a) an input port for receiving an input clock; (b) a linear shift register having a plurality of stages, each of the stages has a data input port, a data output port, and a clock input port, the clock input ports are coupled to the input port, and the stages are connected in series with the data output port of the previous stage coupled to the data input port of the subsequent stage; (c) a feedback loop couples the data output port of the last stage to the data input port of the first stage, and the feedback loop includes a logic gate having an output connected to the data input port of the first stage and a first input connected to the data output port of the last stage and a second input connected to the data output port of the second last stage in the linear shift register; (d) the stages in the linear shift register are operable to shift data at the data input ports to the data output ports and in the feedback loop in response to the input clock; (e) an output port for outputting an output clock signal derived from the data output of the linear shift register; (f) a scan test mode control port; (g) a scan data input port for receiving scan test input data; (h) a scan data output port for outputting scan test output data from the linear shift register; (i) some of the stages including a scan test mode control input, and a scan test data input, the scan test mode control inputs being connected to the scan test mode control port, and at least one of the scan test data inputs being connected to the scan data input port, and the stages being operable to produce scan test output data in response to a scan test mode signal being applied to said scan test mode control port.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.